[Linux-aus] RISC-V

[jon.maddog.hall@gmail.com]

With respect to RISC-V, the idea was to come up with a very small core instruction set (ISA) that follows a reduced instruction set philosophy of creating the hardware.  Normally each instruction takes one clock cycle to operate, as opposed to complicated instruction set computers (CISC) that may take many instruction cycles because they tend to use microcode to execute the instruction.

The core instructions were set up to allow RiSC-V core CPUs to run any modern-day operating system.  This means that they can handle interrupts, do integer math, manage memory, threads of operation, etc.

By having a minimum number of instructions supported the amount of silicon needed to create a chip is minimal, which could mean more chips per silicon wafer.  It also means (in general) that you have less chance of failure on the chip and less heat generated due to having fewer gates (transistors) needed to run the CPU.

The architecture also allows for different extensions to the CPU.   Here is where floating point accelerators can be implemented as well as GPUs, and other extensions that today we tend to think of as part of the system.   I will note that I programed the DEC PDP-8 "back in the day" and it had only eight basic instructions where the system could not even subtract (much less multiply and divide, much less do floating point)....all it could do was add.   By finding the compliment of the number you wish to subtract, adding it to the minuend and discarding the high order bit you could get the result.

Later on I used a PDP-11/70 time-sharing machine that had no floating point hardware.   Every time you encountered a floating point op-code it caused a hardware exception and did the floating point arithmetic with software, then returned from the exception.  If you had a floating point accelerator the same exception happened, but the hardware accelerator did the work a lot faster, so the return was much faster.

All of this is off the top of my head, and I am tired, so please take this as a generality to demonstrate how a hardware extension does not have to be part of the basic ISA.

In any case there are a lot of companies working together to create the base ISA and standardize on the extensions over time in an "Open" way.

A nice project.  My project to create the little computer down in Brazil (caninosloucos.org) is closely following and working on RiSC-V chips.

md

> On 03/24/2023 9:45 PM Adam Nielsen via linux-aus <linux-aus at lists.linux.org.au> wrote:
> 
>  
> > https://www.earth.li/~noodles/blog/2023/02/visionfive-2-impressions.html
> > 
> > Some of this recent RISC-V hardware seems pretty good.
> 
> I had a look into it as I hadn't heard about this before.  So the main
> benefit over something like a Raspberry Pi seems to be that the RISC-V
> architecture is open and doesn't require royalty payments like ARM does.
> 
> One of the big sticking points with the Pi was that the graphics
> hardware was closed for a long time, and it took years before Broadcom
> could be convinced to release documentation for it.  I can't find
> anything about how the graphics hardware works on this board, and
> whether it requires any binary blobs or custom kernel modules.  If
> OpenGL hardware acceleration just works out of the box with a vanilla
> kernel/userspace then that's definitely a plus from an open source
> perspective.
> 
> Cheers,
> Adam.
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